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Meeting the Design Challenges of Nano-CMOS Electronics



The years of "happy scaling" are over: the fundamental challenges that the semiconductor industry faces, at both the technological and design levels, will impinge deeply upon the design of future integrated circuits and systems. This project will bring together leading semiconductor device, circuit and system experts from both academia and industry, along with e-scientists with strong grid expertise. Only by working in close collaboration—and being adequately connected and resourced by e-science and grid technologies—can we understand and tackle the design complexity of nano-CMOS electronics, thereby securing a competitive advantage for the UK electronics industry.

Maturity: Initial Research
Region: UK
Type: Other
Grant Value: £5,300,000.00
Start Date: 01/10/2006
End Date: 30/09/2010
Project Status: funded
Funding Agency: EPSRC

Project Members
PIOther Members
Prof Richard Sinnott
Prof Asen Asenov
Mr Gordon Stewart

Collaborating Organisations
University of Glasgow

Component(s) Project Develops
This project is not associated with any components at present.

Application Area(s) associated with Project
Engineering & Physical


Last Updated: 22 Jun 12 11:02
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